Current buffer compensation topologies for LDOs with improved transient performance

The goal of internal frequency compensation of a low dropout voltage regulator (LDO) is the selection of a small-value, ESR-independent output capacitor. Cascode compensation formed by a common-gate transistor acting as a current buffer, an optional series resistor, and a compensation capacitor creates a dominant pole and a left-halfplane (LHP) zero, allowing adequate phase margin and stable LDO design. To this end, a 1.21 V output, 100 mA, 0.1–10 lF output capacitor, ESR-independent, low voltage LDO using cascode compensation with replica bias is designed and fabricated in a 0.5 lm CMOS process with an area of 0.22 mm. A line regulation of 0.05% V/V, load regulation of 0.001% V/mA and dropout voltage of 220 mV were measured. LDO-specific pole-zero analysis is detailed. In addition to this design, two improved transient response LDO architectures using cascode compensation with split-length transistors are also explored. A Power Good feature is discussed, which enables direct interface between the LDO and a micro-processor.